A radiofrequency (RF) signal may be amplified by a monolithic Multiplying Digital to Analog Converter (MDAC) if a radiofrequency signal is input as a reference signal and a binary code (digital word) is utilized to control, or modulate, the amplitude of the RF output signal. Such an arrangement may be referred to as a Radio Frequency Digital to Analog Converter (RFDAC).
FIG. 1 shows a polar transmitter 100 including an RFDAC circuit 110, and a signal processor circuit 120. The RFDAC circuit 110 is controlled by a digital amplitude signal (am), and driven by a phase modulated RF carrier signal (ap) generated by the signal processor circuit 120. Particularly, an input IQ base band signal (a) is first applied to a digital signal processor 10 which converts the analog IQ base band signal to digital (through Analog to Digital Converter (ADC) 11), and also transforms the signal into amplitude (am) and phase (ap) components (through Rectangular to Polar Converter (RPC) 12). In particular, the ADC 11 digitizes the input analog signal (a), and the RPC 12 translates the digitized wave into polar coordinates. RPC 12 outputs a digitized wave in polar coordinates, which takes the form R, P(sin) and P (cos), for example. In this example, the R coordinate represents an amplitude characteristic (am) of the digitized input wave. The P(sin) and P(cos) coordinates represent a phase characteristic (ap) of the digitized input wave.
The amplitude (am) and phase (ap) characteristics are then transmitted through separate paths in the polar transmitter 100. The amplitude characteristic (am) of the digitized input wave, comprising a digital word (DW) quantized into, for example, bits B0 to BN, with a Most Significant Bit (“MSB”) to Least Significant Bit (“LSB”), is scaled and filtered, by a digital signal processor 13, to form shaped digital pulses which are supplied to the RFDAC circuit 110. The DW may be of varying lengths in various embodiments. In general, the longer the DW the greater the accuracy of reproduction of the input analog wave (a) at the output of the RFDAC circuit 110.
In the exemplary embodiment shown in FIG. 1, the digital amplitude signal (am) is transmitted as an N-bit (e.g., 7-bit) DW through the digital signal processor 13, which scales and filters the digital bits of the DW before providing the digital bits to the RFDAC circuit 110. Each bit of the N-bit DW corresponds to a separate component control line am1-N (e.g., am1-7) in the RFDAC circuit 110. Each of the component control lines am1-N are coupled to a separate control component 22 (e.g., switching transistors 22a-g), which feeds into another transistor 25 (e.g., 25a-g), which is turned ON or OFF depending on the particular bit value on the control component line. For example, if the DW corresponding to the digital amplitude signal (am) is “1110000,” the first three (3) transistors (e.g., 25a-c) will be biased ON, and the last four (4) transistors (e.g., 25d-g) will be biased OFF. In this manner, the amplification of the input analog signal (a) may be effectively controlled, as explained below.
FIG. 5 shows an exemplary implementation of the switching transistors (transistors 22a-g) and segment transistors (transistors 25a-g) of the RFDAC circuit 110. For ease of reference, only one switching transistor 420 and one corresponding segment transistor 430 are shown in FIG. 5. Switching transistor 420 may correspond to one of switching transistors shown in FIG. 1 (e.g., 22a), and thus segment transistor 430 would correspond to the matching segment transistor (e.g., 25a). Switching transistor 420 may comprise a P-channel Metal Oxide Silicon transistor (PMOST), and segment transistor 430 may comprise an Indium Gallium Phosphide (InGaP) heterojunction bipolar junction transistor (HBJT).
The control signal amx shown in FIG. 5 represents one digital bit which is applied to an input port 421 of the switching transistor 420, while an RF signal apx is applied to an input port 431 of the segment transistor 430. An output port 432 is coupled to the collector terminal of the segment transistor 430. This output port 432 port is in turn coupled to the corresponding output ports of the other segments that make up the RFDAC. An input port 425 connects a supply voltage (Vcc) to the source terminal of the switching transistor 420. A direct current (DC) blocking capacitor 440 couples the RF signal apx to the base terminal of the segment transistor 430.
When the source-gate voltage of the switching transistor 420 is less than its turn-on voltage, the switching transistor 420 is OFF and not conducting current, and thus the segment transistor 430 is also OFF since the RF signal current (apx) alone is normally not enough to bias the segment transistor 430 into a region where transistor gain hfe is at its peak value. When the source-gate voltage of the switching transistor 420 exceeds its turn-on voltage, the switching transistor conducts current proportional to its width and length. This current flows into the base terminal of the segment transistor 430 along with the current due to the RF signal apx. At this point, the combination of signal currents (amx and apx) is enough to bias the segment transistor 430 into a peak hfe region, and it is turned ON. The RF signal current (apx) at the output of the segment transistor 430 is amplified by the transistor gain (hfe), and flows out of output port 432.
Returning to FIG. 1, the digital phase signal (ap) is modulated onto a wave by way of Digital to Analog Converter (DAC) 18 and synthesizer 20 before being provided to the RFDAC circuit 110. The synthesizer 20 preferably comprises a Voltage-Controlled Oscillator (VCO) in the exemplary embodiment. The synthesizer 20 provides an output wave (apout), which includes the phase information from the input wave (a). This output wave (apout) has a constant envelope (i.e., it has no amplitude variations, yet it has phase characteristics of the original input wave). The output wave (apout) may be further amplified by amplifier 24 before being provided to the plurality of transistors 25a-g on respective phase signal lines ap1-7.
Regulation of the transistors 25a-g may be accomplished by providing the DW to the control components (e.g., switching transistors 22a-g). Each of the control components 22a-g preferably comprises a transistor acting as a current source. The control components 22a-g are switched by bits of the DW generated from the digital amplitude signal (am). For example, if a bit (e.g., the bit on line am1) of the DW is a logic “1” (e.g., HIGH), the corresponding control component (e.g., 22a) is switched ON, and so current flows from that control component to respective transistor segment (e.g., 25a). Similarly, if the same bit (e.g., the bit on line am1) of the DW is a logic “0” (e.g., LOW), the corresponding control component (e.g., 22a) is switched OFF, and so current is prevented from flowing through that control component to respective transistor segment (e.g., 25a). The current from all transistor segments 25a-g is then combined at the respective transistor outputs lines 26a-g, and provided as an output signal (b) on output signal line 27. Thus, by controlling the value of the DW, the amplification of the digital phase signal (ap) may be accurately controlled using the digital amplitude signal (am), thereby allowing reproduction of an amplified version of the input analog signal (a) at the output of the RFDAC circuit 110.
The resolution of the above-described RFDAC circuit 110 is defined by the number of bits used in the controlling code (i.e., N-bit digital word), while the output equals the phase portion of the input radiofrequency reference signal ‘ap’ multiplied by a fraction equal to the value of the input code divided by the maximum value. For example, the following equation defines the ideal value of the RFDAC output signal:Out=VRF/2N*[20*D0+21*D1+22*D2+ . . . 2N−1*DN−1], where  (Eq. 1)    Out=RFDAC output (voltage or current),    VRF=input reference voltage signal (shown as signal ‘ap’ in FIG. 1),    D0=Least Significant Bit (LSB) Value (e.g., 0 or 1),    D1, 2, etc.=Bit Values Between LSB and MSB (e.g., 0 or 1),    DN−1=Most Significant Bit (MSB) Value (e.g., 0 or 1), and,    N=resolution in bits
Thus, if the resolution of the RFDAC were 3-bit, the output voltage would be equivalent to the input reference voltage (e.g., VRF) multiplied by a factor defined by [(D0+2*D1+4*D2)/8]. Accordingly, the DW “010” corresponds to a multiplication factor of ¼, or in other words, the output voltage is equal to one-fourth (¼) of the input voltage.
An RFDAC monolithic microwave integrated circuit (MMIC) is constructed using an RF compatible process, such as a Gallium Arsenide (GaAs) process, a Silicon Germanium (SiGe) process, or an RF Complementary Metal Oxide Semiconductor (CMOS) process. For example, in an Indium Gallium Phosphide (InGaP) heterojunction bipolar process, the RFDAC is constructed from Heterojunction Bipolar Junction Transistors (HBJTs). A key design parameter for HBJT devices is the unity gain transition frequency (fT). fT is maximum when the HBJT emitter area is optimized for the collector current that flows in the device. Moreover, the emitter area scales with the emitter current. Thus, speed and output current are two parameters, which drive the design of the RFDAC. Other parameters, such as noise and distortion, are also deterministic in the design. Quantization noise requirements set the minimum required resolution (i.e., number of bits in the n-BIT digital word) of the RFDAC.
In almost all integrated circuit designs, speed affects performance while die size affects cost. The physical area of the RFDAC is determined primarily by the maximum output current, and the highest output frequency defined. However, resolution also affects the size, since with any process, the core devices (along with interconnections) require minimum spacing and pitch values. For example, a 2 picofarad (pF) Metal-Insulator-Metal (MIM) capacitor takes up less space if it is constructed as one device than if it were constructed from two (2) 1 pF devices in parallel. Following this rationale, a 12-bit RFDAC with the same full-scale output as a 7-bit RFDAC should take up more area because of the spacing/pitch requirements, but also because there are more input circuits. Each input requires a pad, which increases die area. In addition, more pads require more bond wires and package pins.
Thus, there is presently a need for an RFDAC design which occupies less die space but still permits multi-bit resolutions (e.g., 10-bit digital words or greater).